Research Progress and Application of Approximate Computing Technology in Digital Signal Processing
Keywords:
Approximate computing, Emerging computing paradigms, Digital signal processing, Research progressAbstract
Approximate computing technology has attracted significant attention in the field of signal processing. Complex algorithms and massive data volumes have limited processing speeds and increased hardware consumption in various applications. However, due to the redundancy of signals, precise results are not always necessary, and acceptable results for users are often sufficient. Therefore, the adoption of approximate computing technology can effectively reduce computational load, improve computational efficiency, and enhance system performance. This paper delves into different design levels of approximate computing technology. Firstly, it introduces the characteristics of signal processing applications. Then, it reviews recent research progress in approximate computing technology at both the algorithmic and circuit levels. Additionally, it explores approximate computing solutions in signal processing areas such as communications, video imaging, and radar. Finally, the paper discusses and provides an outlook on the future development directions in this field, offering insights to promote the application of approximate computing technology in signal processing.
References
Liu W, Lombardi F, 2022, Approximate Computing, Springer, Cham, 365–368.
Liu W, Lombardi F, Schulte M, 2020, Approximate Computing: From Circuits to Applications. Proceedings of the IEEE, 108(12): 2103–2107.
Chippa VK, Mohapatra D, Roy K, et al., 2014, Scalable Effort Hardware Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(9): 2004–2016.
Nowick SM, 1996, Design of a Low-Latency Asynchronous Adder Using Speculative Completion. IEE Proceedings Computers and Digital Techniques, 143(5): 301–307.
Lu SL, 2004, Speeding Up Processing with Approximation Circuits. Computer, 37(3): 67–73.
Esposito D, De Caro D, Napoli E, et al., 2015, Variable Latency Speculative Han-Carlson Adder. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(5): 1353–1361.
Seok H, Seo H, Lee J, et al., 2022, A Novel Efficient Approximate Adder Design Using Single Input Pair Based Computation, 2022 19th International SoC Design Conference (ISOCC), Gangneung-si, Korea, 57–58.
Seo H, Kim Y, 2023, A Low Latency Approximate Adder Design Based on Dual Sub-Adders with Error Recovery. IEEE Transactions on Emerging Topics in Computing, 11(3): 811–816.
Manohar PS, Rohan B, Ramana PVS, et al., 2023, Implementation of Carry Look Ahead Adder with 2-Bit Approximate Adder, 2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC), Salem, India, 1543–1547.
Yan A, Wei S, Li Z, et al., 2023, Design of Low-Cost Approximate CMOS Full Adders, 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, USA, 1–5.
Lagidi P, Iswarya A, Rajesh G, et al., 2021, Design of 16-Bit and 32-Bit Approximate Full Adder Using Majority Logic, 2021 2nd Global Conference for Advancement in Technology (GCAT), Bangalore, India, 1–5.
Liu B, Xue A, Wang Z, et al., 2023, A Reconfigurable Approximate Computing Architecture with Dual-VDD for Low-Power Binarized Weight Network Deployment. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(1): 291–295.
Mitchell JN, 1962, Computer Multiplication and Division Using Binary Logarithms. IRE Transactions on Electronic Computers, EC-11(4): 512–517.
Kim MS, Del Barrio AA, Oliveira LT, et al., 2019, Efficient Mitchell’s Approximate Log Multipliers for Convolutional Neural Networks. IEEE Transactions on Computers, 68(5): 660–675.
Nunziata I, Zacharelos E, Saggese G, et al., 2022, Approximate Recursive Multipliers Using Carry Truncation and Error Compensation, 2022 17th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Villasimius, Italy, 137–140.
Waris H, Wang C, Liu W, et al., 2022, Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers. IEEE Transactions on Emerging Topics in Computing, 10(1): 507–513.
Shankar RG, Ananthi DR, 2023, Approximate Booth Multipliers Using Compressors and Counter, 2023 International Conference on Inventive Computation Technologies (ICICT), Lalitpur, Nepal, 1658–1662.
Liu B, Cai H, Zhang Z, et al., 2023, Multiplication Circuit Architecture for Error-Tolerant CNN-Based Keywords Speech Recognition. IEEE Design & Test, 40(3): 26–35.
Sayadi L, Timarchi S, Sheikh-Akbari A, 2023, Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4: 2 Compressors. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(4): 1649–1659.
Zhang M, Nishizawa S, Kimura S, 2023, Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(5): 1714–1718.
Xie N, Zhang R, Yan H, et al., 2022, Compressors Evolution Based High Speed and Energy Efficient Approximate Signed Multiplier, 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nanjing, China, 1–3.
Tong JYF, Nagle D, Rutenbar RA, 2000, Reducing Power by Optimizing the Necessary Precision/Range of Floating-Point Arithmetic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3): 273–286.
Eilert J, Ehliar A, Liu D, 2004, Using Low Precision Floating Point Numbers to Reduce Memory Cost for MP3 Decoding, 2004 IEEE 6th Workshop on Multimedia Signal Processing, Siena, Italy, 119–122.
Zhang H, Putic M, Lach J, 2014, Low Power GPGPU Computation with Imprecise Hardware, 51st ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, USA, 1–6.
Yin P, Wang C, Liu W, et al., 2016, Design and Performance Evaluation of Approximate Floating-Point Multipliers, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 296–301.
Savio MMD, Deepa T, Dharshini PD, et al., 2023, Design and Implementation of Approximate Divider for Error-Resilient Image Processing Applications, 2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), Trichirappalli, India, 1–5.
Shriram A, Tiwari A, Anil Kumar U, et al., 2022, Power Efficient Approximate Divider Architecture for Error-Resilient Application, 2022 IEEE6th Conference on Information and Communication Technology (CICT), Gwalior, India, 1–6.
Wu Y, Jiang H, Ma Z, et al., 2022, An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(7): 2655–2668.
Saadat H, Javaid H, Parameswaran S, 2019, Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias, 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, 1–6.
Liu W, Xu T, Li J, et al., 2022, Design of Unsigned Approximate Hybrid Dividers Based on Restoring Array and Logarithmic Dividers. IEEE Transactions on Emerging Topics in Computing, 10(1): 339–350.
Wuerdig RN, Sartori MLL, Abreub A, et al., 2022, Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, USA, 1269–1273.
Mishra V, Pandey D, Singh S, et al., 2022, ART-MAC: Approximate Rounding and Truncation Based MAC Unit for Fault-Tolerant Applications, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, USA, 1640–1644.
Esposito D, De Caro D, Napoli E, et al., 2017, On the Use of Approximate Adders in Carry-Save Multiplier-Accumulators, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, USA, 1–4.
Wang Z, Wei Q, Xue A, et al., 2022, Low-Power Computing Unit Based on Heterogeneous Approximate Structure for Binary Convolutional Neural Network, 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nanjing, China, 1–3.
Di Meo G, Saggese G, Strollo AGM, et al., 2023, Approximate MAC Unit Using Static Segmentation. IEEE Transactions on Emerging Topics in Computing, (99): 1–12.
Liu B, Zhang Z, Cai H, et al., 2022, Self-Compensation Tensor Multiplication Unit for Adaptive Approximate Computing in Low-Power CNN Processing. Science China Information Sciences, 65(4): 149403.
Liu B, Zhang R, Shen Q, et al., 2023, W-AMA: Weight-Aware Approximate Multiplication Architecture for Neural Processing. Computers and Electrical Engineering, (111): 108921.
Jiang H, Liu L, Jonker PP, et al., 2019, A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(1): 313–326.
Esposito D, Di Meo G, De Caro D, et al., 2018, Quality-Scalable Approximate LMS Filter, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Bordeaux, France, 849–852.
Di Meo G, De Caro D, Petra N, et al., 2022, A Novel Low-Power DLMS Adaptive Filter with Sign-Magnitude Learning and Approximated FIR Section, 2022 17th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), Villasimius, Italy, 217–220.
Monteiro M, Seidel I, Grellert M, et al., 2022, Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection, 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), Puerto Varas, Chile, 1–4.
Bergland G, 1969, Fast Fourier Transform Hardware Implementations: An Overview. IEEE Transactions on Audio and Electroacoustics, 17(2): 104–108.
Elango K, Muniandi K, 2020, VLSI Implementation of an Area and Energy Efficient FFT/IFFT Core for MIMO-OFDM Applications. Annals of Telecommunications, 75(5/6): 215–227.
Liu B, Ding X, Cai H, et al., 2021, Precision Adaptive MFCC Based on R2SDF-FFT and Approximate Computing for Low-Power Speech Keywords Recognition. IEEE Circuits and Systems Magazine, 21(4): 24–39.
Liu W, Liao Q, Qiao F, et al., 2019, Approximate Designs for Fast Fourier Transform (FFT) with Application to Speech Recognition. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(12): 4727–4739.
Chen WH, Smith C, Fralick S, 1977, A Fast Computational Algorithm for the Discrete Cosine Transform. IEEE Transactions on Communications, 25(9): 1004–1009.
Potluri US, Madanayake A, Cintra RJ, et al., 2014, Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(6): 1727–1740.
Da Silveira TLT, Canterle DR, Coelho DFG, et al., 2022, A Class of Low-Complexity DCT-Like Transforms for Image and Video Coding. IEEE Transactions on Circuits and Systems for Video Technology, 32(7): 4364–4375.
Xing Y, Zhang Z, Qian Y, et al., 2018, An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 1–4.
Cai L, Qian Y, He Y, et al., 2021, Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 1–4.
Janhunen J, Pitkanen T, Silven O, et al., 2011, Fixed-and Floating-Point Processor Comparison for MIMO-OFDM Detector. IEEE Journal of Selected Topics in Signal Processing, 5(8): 1588–1598.
Amin-Nejad S, Basharkhah K, Gashteroodkhani TA, 2019, Floating Point Versus Fixed Point Tradeoffs in FPGA Implementations of QR Decomposition Algorithm. European Journal of Electrical Engineering and Computer Science, 3(5): 127.
Hu Y, Koibuchi M, 2021, Accelerating MPI Communication Using Floating-Point Compression on Lossy Interconnection Networks, 2021 IEEE 46th Conference on Local Computer Networks (LCN), Edmonton, Canada, 355–358.
Park J, Choi JH, Roy K, 2010, Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(5): 787–793.
Snigdha FS, Sengupta D, Hu J, et al., 2016, Optimal Design of JPEG Hardware Under the Approximate Computing Paradigm, 2016 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, USA, 1–6.
Pu Y, De Gyvez JP, Corporaal H, et al., 2010, An Ultralow-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS with Sub/Near Threshold Supply Voltage. IEEE Journal of Solid-State Circuits, 45(3): 668–680.
Fang J, Xu Z, Zhang B, et al., 2014, Fast Compressed Sensing SAR Imaging Based on Approximated Observation. IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, 7(1): 352–363.
Jiang C, Zhang B, Fang J, et al., 2014, Efficient ℓq Regularisation Algorithm with Range-Azimuth Decoupled for SAR Imaging. Electronics Letters, 50(3): 204–205.
Li B, Liu F, Zhou C, et al., 2018, Mixed Sparse Representation for Approximated Observation-Based Compressed Sensing Radar Imaging. Journal of Applied Remote Sensing, 12(3): 035015.
Li B, Liu F, Zhou C, et al., 2017, Phase Error Correction for Approximated Observation-Based Compressed Sensing Radar Imaging. Sensors, 17(3): 613.